1. Field of the Invention
The present invention generally relates to a photodetecting circuit such as a photoconductive switch and an optical type position detecting apparatus where light illuminated from a light emitting element is photoelectrically detected via detecting space by a light receiving element, and, more particularly, to a photodetecting circuit capable of preventing erroneous operations of the photodetecting circuit under higher intensity of peripheral light.
2. Description of the Related Art
In a photoconductive switch and an optical type position detecting apparatus, a light emitting element is positioned either, directly opposite to a light receiving element, or indirectly opposite to the light receiving element by employing a reflecting mirror and an optical fiber so as to form an optical beam in detecting space. Then, an output signal such as an interruption signal and a position signal is obtained, which represents such a fact that an optical beam originated from the light emitting element is not transferred to the light receiving element, by detecting the interruption of the optical beam.
Normally, a visual, or an infrared light emitting diode is employed as the light emitting element, and a phototransistor, or a photodiode is utilized as the light receiving element in the photoconductive apparatus.
Since the photodetecting circuit of the photoconductive apparatus includes opening space for detecting the incident light, it may be adversely influenced by not only the light transferred from the light source, but also unwanted light, e.g., the illumination around the opening space (i.e., peripheral light). Various types of the conventional methods for eliminating the peripheral light have be so far proposed. In, for instance, Japanese examined (KOKOKU) patent application No. 61-25161, there is disclosed the threshold level controlling type photodetecting circuit.
The above-described published conventional photodetecting circuit will now be summarized with reference to drawings.
FIG. 3 is a circuit diagram of the prior art photodetecting circuit, and FIG. 4 illustrates waveforms to explain various operations of the circuit shown in FIG. 3.
To describe the circuit arrangement shown in FIG. 3, reference numeral 1 denotes an inverting logic circuit; reference numeral 2 indicates an analog comparator circuit (referred to as "a comparator circuit"); a symbol "CL" represents a synchronizing signal line; a symbol "C2" is a capacitor; a symbol "LED" indicates a light emitting diode; a symbol "PTR" represents a light receiving element; a symbol "Q" is a transistor; symbols "R3" to "R8" are resistors; a symbol "S" represents a switching circuit; and a symbol "Vcc" indicates a power supply line.
In the circuit shown in FIG. 3, one terminal of a series circuit constructed by the light emitting diode LED and the resistor R3 is connected to a positive power supply line, whereas the other terminal thereof is connected to a collector of an NPN bipolar transistor Q. To a base electrode of this transistor Q, one end of the resistor R4 is connected, the other end of which resistor R4 is connected to the output terminal of the inverting logic circuit 1 (will be discussed later). The base electrode of the transistor Q is grounded via the resistor R5. An emitter of this transistor Q is also grounded. The above-described circuit arrangement will drive the light emitting diode LED when the output of the inverting logic circuit 1 becomes a high level.
Then, the circuit arrangement of the light receiving circuit will now be described. The light receiving element PTR is an NPN type bipolar phototransistor. A collector of this bipolar phototransistor is connected to the positive power supply line Vcc, whereas a base electrode of the phototransistor functioning as the light detecting section, is so arranged as to receive the light emitted from the light emitting diode (element) LED. An emitter of this light receiving element PTR is grounded via the resistor R6. A junction between this emitter and the resistor R6 is connected to each one end of the resistor R7 and the switching circuit S. The other end of the resistor R7 is connected to a non-inverting input (+) of the comparator circuit 2. This non-inverting input (+) of the comparator circuit 2 is grounded via the resistor R8. A signal having a value corresponding to the light receiving amount of the light emitting element PTR is divided by the resistors 7 and 8 and then supplied to the non-inverting input terminal (+).
The other end of the switching element S and one terminal of the capacitor C2 are, one the other hand, connected to the inverting input (-) of this comparator circuit 2. As this switching element S, an analog switch arranged by a field effect transistor (FET) is employed. The switching element S has first and second terminals which are conductive in both ways, and a third terminal. When a high level voltage is applied to the third terminal of the switching element S, a minimum impedance is present between the first and second terminals thereof. The first terminal of the switching element "S" is connected to the emitter of the above-described light emitting element PTR, and the second terminal thereof is connected to the inverting input (-) of the above-mentioned comparator circuit 2, and furthermore, the third terminal thereof is connected to the synchronization signal line CL in combination with the input of the above-identified inverting logic circuit 1. Since the inverting input (-) of the comparator circuit 2 is grounded via the above-described capacitor C2, the voltage produced while the switching element "S" is closed, is held by the capacitor C2 which is so arranged as a sample-and-hold circuit fuctioning when the switching element "S" is opened.
The comparator circuit 2 compares the noninverting input (+) with the inverting input (-) supplied via the sample-and-hold circuit, and then outputs a high level signal when the voltage of the non-inverting input (+) exceeds the inverting input (-), and outputs a low level signal when the voltage of the inverting input (-) is lower than the inverting input.
Operations of the conventional photodetecting circuit shown in FIG. 3 will now be described with reference to the various waveforms illustrated in FIG. 4.
As illustrated in FIG. 4a, a positive rectangular pulse having a predetermined period and a predetermined crest value is input as an input signal to the synchronizing signal line CL. Based upon this clock pulse (a), both the switching circuit "S" and the inverting amplifier 1 supply, as indicated by a dotted line of FIG. 4f, the output signal detected by the light receiving element PTR to the inverting input (-) of the comparator circuit 2, and also turn on and off the light emitting diode LED in a form of a rectangular pulse, as illustrated by a dotted shape of FIG. 4c. It is assumed that the light such as sunlight and lamp light having the intensity (b) of the peripheral light, as shown in FIG. 4(b), is incident upon the light receiving element PTR under the condition of the detecting space where the optical signal emitted from the light emitting diode LED can reach the light receiving element PTR. Under the above-identified condition, the detection signal (e) of the light receiving element PTR acquired by detecting the light having the intensity of the waveform, as shown in FIG. 4d, is divided by the resistors R7 and R8, and the resultant voltage is applied to the non-inverting input (+) of the comparator circuit 2, as illustrated by a solid line of "A" in FIG. 4f.
The voltage is input via the sample-and-hold circuit to the inverting input (-) of the comparator circuit 2 under the following condition. That is to say, this voltage is applied to this comparator circuit 2 while the signal output condition obtained by receiving the peripheral light very close to the light receiving element PTR during the turn-off of the light emitting diode LED, is held only when the light emitting diode LED is turned on.
As a consequence, when the voltage signal "A" being applied to the non-inverting input (+) exceeds the voltage signal "B" being applied to the inverting input (-) of the comparator circuit 2, the high-leveled signal g1 is output as illustrated in FIG. 4g, which represents the non-detection condition. However, even if the peripheral interference light is incident upon the light receiving element PTR, no high-leveled output signal indicating the non-detection condition is produced. This is because only the voltage component divided by the above-described resistors R7 and R8 is applied to the inverting input (-) of the comparator circuit 2, which is lower than the voltage being applied to the non-inverting input (+) thereof under the condition that the optical signal originated from the light emitting diode LED cannot reach the light receiving element PTR.
The above-described conventional photodetecting circuit has however the following great drawbacks.
That is to say, when the peripheral interfering light is incident upon the light receiving element PTR, as illustrated by a range "C" in FIG. 4e, the emitter current of the light receiving element, i.e., phototransistor PTR is saturated at an approximate value defined by the power supply voltage Vcc and the resistor R6, so that the voltage (referred to the symbol "A" in FIG. 4f) being applied to the non-inverting input (+) does not exceed the voltage (referred to the symbol "B" in FIG. 4f) of the inverting input (-) of the comparator circuit 2 although the light come from the light emitting diode LED has reached the light receiving element PTR. Accordingly, since the low-leveled output signals g2 and g3 (see FIG. 4g) representative of the detection condition are output, the erroneous operation will occur inevitably.
It is, therefore, a primary goal of the present invention to provide a photodetecting circuit which can avoid such an erroneous operation that the signal representative of the non-detecting condition is mistakenly output in the conventional circuit when the peripheral interfering light having the higher intensity is received under the detecting condition, and also prevent another erroneous operation that the signal indicating the non-detecting condition is erroneously output in the prior art circuit when the peripheral interfering light having the higher intensity is received under the non-detecting condition.